parallel input

The FPGA hardcore resources were used less as far as possible during the whole system designed, and the multiplier which occupy more resources and had slower speed was not used, parallel input and pipelining technology were used to improve the running speed of circuit.

整个系统设计时都尽量少用FPGA的硬核资源，并且没有使用占用资源多，速度较慢的乘法器的使用，同时还采用了并行输入方式和流水线技术来提高电路的运行速度。

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Here is the communication protocol used in half-duplex asynchronous serial communication, parallel input serial output sampling.

在这里的通信协议采用的是 半双工 异步串行通信方式, 并行输入串行输出采样.

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